WEEK 4 TASK 9 compare results with results of other groups

In the high-k gate stacks, the more Hf contains, the higher oxide relative permittivity, the thinner equivalent oxide thickness, the more negative oxide charge density.

So that the high-k material can increase the physical thickness without increasing the electrical oxide thickness, and using high-k material to replace the transistor's silicon dioxide gate dielectric can improve circuit performance.

WEEK 3 TASK 8, find the oxide charge density at the flatband condition and at the midgap condition

First of all, the relationship between gate voltage and surface potential is defined below:

The figure (1) is an example of "Effects of bulk oxide charge for an n-type MOS-C", it is very similar to the p-type condition. 

(1)

The figure (2) is the comparison ideal and real midgap of p-type condition, 

(2)

Essentially, there have two conditions need to be concerned. 

Flatband condition:

the idear VG is 0 V, and the real Vg has been calculated in the task 6 which is 0.265 V, so that the delta V is -0.265 V.

=-1.57527* 10^16  (m^-2) =-1.57527*10^12 (cm^-2)

Midgap condition:
=0.3172 eV

the ideal VG is

=0.3316V
so that deltV is -0.4864

=-2.8913*10^16  (m^-2)  = -2.8913*10^12 (cm^-2)

WEEK 3 TASK 7 calculate the midgap voltage

As this p-type gate voltage becomes positive, majority carriers which is holes are forced away from the surface of the semiconductor. As a consequence of that, a depletion region was formed.

Under this condition, the work function of semiconductor Φs is equal to Fermi energy Φ_F

Where ni = 1 * 10^10 cm^-3 and Vt = 25 mV at a temperature of 300K.

So that 

Corresponding to the CV curve in task 1, the mid-gap Voltage can be demonstrated is 0.818 V.

WEEK 2 TASK 6, calculate the flatband voltage.

The accumulation capacitance becomes smaller and has the effect of reducing the measured capacitance as VG is gradually increased. on the other hand, when VG is equal to zero voltage(ideal case) or near to zero voltage(actual case), the condition of flatbands exists.

The equivalent circuit at flat-band shows below:

The semiconductors' capacitor is defined by the Debye length thus:

Then, the Debye length is given by:

So that

Compare with the curve in task 1,

when C=113.41 pF, V=0.265 V

that means the flatband voltage can be calculated as 0.265 V. 

WEEK 2 TASK 5, calculate the work function difference assuming a gold (Au) gate.

This is the energy band diagram explaining work function.

For a metal,  is a constant that can be measured; =5.1 eV for gold (Au).

for a semiconductor, the work function depends on the doping level and is given byas denoted in the figure. where ni(Si)=1*10^16 m^-3 and Vt=kT/q=25mV at temperature of 300K

So that

Metal: 

Semiconductor:

Difference: 

WEEK 2 TASK 4, determine the doping density of the silicon substrate

The minimum capacitance Cmin is given as the series contribution of oxide and semiconductor:

Where Cox is equal to Cmax which has been calculated in task2.

Cdep can be calculated as follow:
The equivalent circuit for depletion can be measured two capacitors in series.

and assuming a uniformly doped semiconductor, we have

where W is the depletion width. Width increases with gate voltage so the capacitance Cdep decreases and so does the measured capacitance.

can be calculated as follow:

This is the energy band diagram explaining work function.

Where ni = 1 * 10^10 cm^-3 and Vt = 25 mV at a temperature of 300K.

While Cmin can also be read in the C-V curve which in task 1.

The extraction of doping density is given by:

where A is calculated in task 2, k is Boltzmann's constant, T is temperature of 300K. q, epsilon o, epsilon s and ni are given in the project specification

So that the doping density is

the answer NA cannot be calculated directly, while we can applying the method of Newton ralphson to plot two curves using matlab and then find the value of interconnection point which is the answer.

WEEK 1 TASK 3, find the equivalent oxide thickness (EOT)

An Equivalent oxide thickness is a distance that indicates how thick a silicon oxide film would need to be to produce the same effect as the high-k material being.

So that

WEEK 1 TASK 2, determine the oxide relative permittivity

In task 1, we identify the type of substrate which is p-type, so that the oxide capacitor is measured in the accumulation region where the corresponding C-V curve is nearly flat and the capacitor is nearly constant. Therefore, the MOS capacitor can be represented by an equivalent circuit comprising the oxide capacitor and the accumulation layer which are in series:

Due to a very high value for Cacc, we only observes the value of Cox for the measured capacitance in the accumulation region of a C-V plot. This enables the thickness of the oxide to be extracted:

where Cox is the capacitance per unit area and Ac is the capacitor area.

Cox is formed by two layer which are SiO2 and high-k

From TASK 1, the Cmax is 1081 pF, and from project specification, the diameter of MOS capacitors is 0.38 mm.

So that, we got