Background

1 MOS Capacitor

Figure 1 shows (a) perspective view and (b) cross-section of an
metal-oxide-semiconductor (MOS) capacitor.

Fabrication steps of a silicon MOS capacitor
 Thermal oxidation of a wafer to form a SiO2 layer on Si surface.
 Deposit a metal layer on SiO2 and define the metal plate.
 An ohmic contact is made on the bottom of the Si wafer.

V is the applied voltage on the metal plate (positive or negative with respect to the ohmic contact).

d is the thickness of the oxide.

MOS (metal-oxide-semiconductor) capacitor is the most useful device to study semiconductor surface properties, it is also a key building block for MOSFET and related devices.

Reference
S. M. Sze and M. K. Lee, Semiconductor Devices: Physics and Technology, 3rd Edition, Wiley, Hoboken (2013) chapter 5, page 162

2 High-k Dielectrics

"High-k" stands for high dielectric constant, a measure of how much charge a material can hold. Air is the reference point for this constant and has a "k" of 1.0. Silicon dioxide (the "old-fashioned" gate material) has a "k" of 3.9. "High-k" materials, such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2) and titanium dioxide (TiO2) have "k" values higher than 3.9.

Using a "high-k" (Hi-k) material to replace the transistor's silicon dioxide gate dielectric can improve circuit performance.

why using high k?
Gate leakage in a modern transistor occurs through a process called "quantum mechanical tunneling." Under normal circumstances, all the electrons are on the "upstream" side of the gate (picture the gate as a dam, and electrons as water trapped behind the dam). Quantum mechanical tunneling occurs when the gate dimension is so thin that the electrons (or holes) have a certain statistical probability of being on the "downstream" side of the gate - without actually sloshing over the gate. In modern transistors, the gate thickness is about five atomic layers. The thinner the gate, the larger the tunneling current and the higher the leakage power.

The tunneling current can be reduced by thickening the gate. The problem here is that increasing the physical gate thickness increases the electrical oxide thickness, and thus reduces the transistor performance. The ideal solution would be to increase the physical thickness WITHOUT increasing the electrical oxide thickness. Amazingly enough, this is possible by increasing the "k" (or dielectric constant) of the material. A "higher-k" material can be physically thicker (by approximately the ratio of the old/new "k") without being electrically thicker.

Reference
http://www.intel.com/pressroom/kits/advancedtech/doodle/ref_HiK-MG/high-k.htm